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PRODUCT SPECIFICATIONS
(R)
Integrated Circuits Group
LH28F008SCR-L85
Flash Memory
8M (1M x8)
(Model No.: LHF08CH2)
Spec No.: EL104029B Issue Date: February 1, 1999
SHARP
LHF08CH2
l Handle
this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company.
l When using the products covered herein, please observe
the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein application areas. When using in Paragraph (Z), even for the precautions given in Paragraph in Paragraph (3). are designed and manufactured for the following the products covered herein for the equipment listed following application areas, be sure to observe the (2). Never use the products for the equipment listed
*Office electronics l instrumentation and measuring equipment .Machine tools @Audiovisual equipment *Home appliance l Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands hiah reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. *Control and safety devices for airplanes, trains, automobiles, transportation equipment l Mainframe computers aTraffic control systems @Gas leak detectors and automatic cutoff devices 6escue and security equipment @Other safety devices and safety equipment,etc. and other
(3) Do not use the products covered herein for the following equipment which demands extremelv hiqh performance in terms of functionality, reliability, or accuracy. *Aerospace equipment *Communications equipment for trunk lines *Control equipment for the nuclear power industry l Medical equipment related to life support, etc. (4) Please direct all queries and comments three Paragraphs to a sales representative *Please direct all queries regarding of the company. regarding the interpretation of the company. of the above
the products covered
herein to a sales representative
Rev.l.l
SHARP
LHFOSCH2 1
CONTENTS
PAGE I .O INTRODUCTION ................................................... ...................................................... 1 .l New Features 1.2 Product Overview.. .............................................. OF OPERATION.. ........................... 3 3 3 7 7 8 8 8 8 8 9 9 9 12 12 12 12 12 13 PAGE 5.0 DESIGN CONSIDERATIONS ............................. .2? 5.1 Three-Line Output Control ................................ .2? 5.2 RY/BY# and Block Erase, Byte Write and Lock-Bit 25 Configuration Polling ........................................... 5.3 Power Supply Decoupling.. ................................ 24 5.4 V,, Trace on Printed Circuit Boards.. ............... .2f 24 5.5 v,,, v,,, RP# Transitions ................................. 5.6 Power-Up/Down Protection ................................ 24 5.7 Power Dissipation ............................................. .24
2.0 PRINCIPLES
2.1 Data Protection ................................................... 3.0 BUS OPERATION ................................................. 3.1 Read ................................................................... 3.2 Output Disable .................................................... 3.3 Standby.. ............................................................. .............................................. 3.4 Deep Power-Down 3.5 Read Identifier Codes Operation.. ....................... 3.6 Write .................................................................... 1.0 COMMAND DEFINITIONS. ................................... 4.1 Read Array Command.. ..................................... 4.2 Read Identifier Codes Command ...................... 4.3 Read Status Register Command.. ..................... 4.4 Clear Status Register Command.. ..................... 4.5 Block Erase Command.. .................................... 4.6 Byte Write Command ........................................
6.0 ELECTRICAL
..................... .2E 6.1 Absolute Maximum Ratings ............................... 25 6.2 Operating Conditions ......................................... 25 6.2.1 Capacitance ................................................. 25 6.2.2 AC Input/Output Test Conditions.. ............... .2E ........................................ 27 6.2.3 DC Characteristics 6.2.4 AC Characteristics - Read-Only Operations .2E 6.2.5 AC Characteristics - Write Operations.. ....... .34 6.2.6 Alternative CE#-Controlled Writes.. ............. .3E ........................................ 6.2.8 Block Erase, Byte Write and Lock-Bit Configuration Performance.. ........................ 6.2.7 Reset Operations .3E .3E .40 40 ..4 1
SPECIFICATIONS..
4.7 Block Erase Suspend Command.. ..................... 13 4.8 Byte Write Suspend Command.. ....................... 14 4.9 Set Block and Master Lock-Bit Commands.. ..... 14 4.10 Clear Block Lock-Bits Command.. ................... 15
7.0 ADDITIONAL 7.1 Ordering 8.0 PACKAGE
............................ Information .......................................... AND PACKING SPECIFICATIONS
INFORMATION
J Rev. 1.0
LHF08CH2
2
LH28F008SCR-L85 8-MBIT (1 MB x 8) SmartVoltage Flash MEMORY
n SmartVoltage Technology - 2.7V(Read-Only), 3.3V or 5V VCC - 3.3V, 5V or 12V Vpp n High-Performance Read Access Time - 85ns(5V-c0.25V), 90ns(5Vk0.5V), 120ns(3.3V=0.3V), 150ns(2.7V-3.6V) n Operating Temperature - 0C to +7O"C n High-Density Symmetrically-Blocked Architecture - Sixteen 64-Kbyte Erasable Blocks n Low Power Management - Deep Power-Down Mode - Automatic Power Savings Mode Decreases ICC in Static Mode I Automated Byte Write and Block Erase - Command User Interface - Status Register SRAM-Compatible Write Interface n n Enhanced Automated Suspend Options - Byte Write Suspend to Read - Block Erase Suspend to Byte Write - Block Erase Suspend to Read Enhanced Data Protection Features - Absolute Protection with Vpp=GND - Flexible Block Locking - Block Erase/Byte Write Lockout during Power Transitions Extended Cycling Capability - 100,000 Block Erase Cycles - 1.6 Million Block Erase Cycles/Chip Industry-Standard Packaging - 40-Lead TSOP (Reverse Bend) ETOXTM* Nonvolatile Flash Technology
n
n
n n
CMOS Process (P-type silicon substrate) Not designed hardened or rated as radiation
n I
SHARP's LH28F008SCFGL85 Flash memory with SmartVoltage technology is a high-density, low-cost, nonvolatile, ,ead/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage ind extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory :ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F008SCR-L85 offers three levels of protection: absolute protection with V,, at ;ND, selective hardware block locking, or flexible software block locking. These alternatives give designers Jltimate control of their code security needs. The LH28F008SCR-L85 is manufactured on SHARP's 0.38um ETOXTM process technology. It come in ndustry-standard package: the 40-lead TSOP, ideal for board constrained applications. Based on the 28F008SA architecture, the LH28F008SCR-L85 enables quick and easy upgrades for designs demanding the state-of-the-art. ETOX is a trademark of Intel Corporation.
Rev.1.11
SHARf=@
LHF08CH2 3
1 INTRODUCTION
This datasheet contains LH28F008SCRL85 specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F008SCRL85 Flash memory documentation also includes application notes and design tools which are referenced in Section 7.
SmartVoltage technology provides a choice of V,, and V,, combinations, as shown in Table 1, to meet system performance and power expectations. 2.7V Vc, consumes approximately one-fifth the power of 5V Voo. But, 5V Voo provides the highest read performance. V,, at 3.3V and 5V eliminates the need for a separate 12V converter, while V,,=12V maximizes block erase and byte write performance In addition to flexible erase and program voltages the dedicated V,, p in g ives complete data protectior when V,, I VPPLK. Table 1. V,, > and VP, Voltage Combinations
1.1 New Features
The LH28F008SCRL85 SmartVoltage Flash memory maintains backwards-compatibility with SHARP's ?8F008SA. Key enhancements over the 28F008SA nclude: *SmartVoltage *Enhanced *In-System Technology
Suspend Capabilities Block Locking
NOTE: 1. Block erase, byte write and lock-bit configuratior operations with Vcoc3.OV are not supported. Internal and Vcc automatically configures read and write operations.
VP,
30th devices share a compatible pinout, status ,egister, and software command set. These similarities enable a clean upgrade from the !8F008SA to LH28F008SCR-L85. When upgrading, t is important to note the following differences: *Because of new feature support, the two devices have different device codes. This allows for software optimization.
detection Circuit4 the device for optimizec
l VPPLK
has been lowered from 69 to 1.5V to support 3.3V and 5V block erase, byte write, and lock-bit configuration operations. The V,, voltage transitions to GND is recommended for designs that switch V,, off during read operation. technology,
A Command User Interface (CUI) serves as the interface between the system processor and interna operation of the device. A valid command sequence written to the CUI initiates device automation. Ar internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuratior operations. A block erase operation erases one of the device's 64-Kbyte blocks typically within 0.3 s (5V V,,, 12V V,,) independent of other blocks. Each block can be independently erased 100,000 times (1.6 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. Writing memory data is performed in byte increments typically within 6 us (5V Voo, 12V VP,). Byte write suspend mode enables the system to read data or execute code from any other flash memory array location.
*To take advantage of SmartVoltage allow V,, connection to 3.3V or 5V.
I.2 Product
Overview
`he LH28F008SCR-L85 is a high-performance 8-Mbit ;martVoltage Flash memory organized as 1 Mbyte of I bits. The 1 Mbyte of data is arranged in sixteen ICKbyte blocks which are individually erasable, jckable, and unlockable in-system. The memory lap is shown in Figure 3.
Rev. 1.2
SHAM=
LHF08CH2 4
Individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. Lock-bit configuration operations (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands) set and cleared lock-bits. The status register indicates when the WSM's block erase, byte write, or lock-bit configuration operation is finished. The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is oerforming a block erase, byte write, or lock-bit zonfiguration. RY/BY#-high indicates that the WSM is ?eady for a new command, block erase is suspended [and byte write is inactive), byte write is suspended, or the device is in deep power-down mode.
The access time is 85 ns (t,.,,,*,,) over the commercia temperature range (0C to +70X) and Vco supply voltage range of 4.75V-5.25V. At lower Vco voltages, the access times are 90 ns (4.5V-5SV), 120 ns (3.OV-3.6V) and 150 ns (2.7V-3.6V). The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical I,,, current is 1 mA at 5V Vcc. When CE# and RP# pins are at Voc, the ICC CMOS standby mode is enabled. When the RP# pin is al GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. The device is available in 40-lead TSOP (Thin Small Outline Package, 1.2 mm thick, Reverse Bend). Pinout is shown in Figure 2.
Rev.1.0
SHARP
LHF08CH2 5
r
CE# \VE# (X3 RPb'
. . + 3*
. . . . . . . . . . fff
Figure 1. Block Diagram
NC NC WE# OE# RY/BY#
DQ7 DQ6 DQ5 DQ4 vcc
49
A16 A17 Al6 A15 A14 A13 A12
GND GND DQ3
40-LEAD TSOP STANDARD PINOUT 1Omm x 20mm TOP VIEW
CE# vcc
VPP
RP#
41
DQ2 DQl DQo
2
A2 A3
40 A9 A6
A7 A6 A5 A4
Figure 2. TSOP 40-Lead
Pinout
(Reverse
Bend)
Rev. 1 .ll
Sl-iARP
LHF08CH2 6
1
r
Symbol A&
9
Type
INPUT INPUT/ OUTPUT
DQc-DQ,
CE#
INPUT
RP#
INPUT
OE# WE#
INPUT INPUT
RY/BY#
OUTPUT
"PP
SUPPLY
"CC
SUPPLY
GND NC
SUPPLY
Table 2. Pin Descriptions Name and Function ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. DATA INPUT/OUTPUTS: Inputs data and commands durino CUI write cycles; outputs data during memory array, status register, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CHIP ENABLE: Activates the device's control logic, input buffers, decoders, and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provides data protection during power transitions. Exit from deep power-down sets the device to read array mode. RP# at V,, enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. RP#=V,, overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. Block erase, byte write, or lock-bit configuration with VIHRev. 1.0
LHF08CH2
7
2 PRINCIPLES
OF OPERATION
FFFFF I F0000 EFFFF EOOOO DFFFF DO000 CFFFF coooo BFFFF BOOW AFFFF AOODO BFFFF 9Qooo 6FFFF Kmo 7FFFF 70000 BFFFF 60000 SFFFF sow0 4FFFF 40000 JFFFF 30000 PFFFF 2oooo 1 FFFF 1oocil OFFFF
The LH28F008SCR-L85 SmartVoltage Flash memory includes an on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with RAM-Like interface timings. After initial device power-up or return from deep power-down mode (see Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the V,, voltage. High voltage on V,, enables successful block erasure, byte writing, and lock-bit configuration. All functions associated with altering memory contents-block erase, byte write, Lock-bit configuration, status, and identifier codes-are accessed via the CUI and verified through the status register. Commands written using standard are microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, byte write, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latch during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. nterface software that initiates and polls progress of ,lock erase, byte write, and lock-bit configuration can Ie stored in any block. This code is copied to and executed from system RAM during flash memory Jpdates. After successful completion, reads are igain possible via the Read Array command. Block erase suspend allows system software to suspend a Ilock erase to read or write data from any other Ilock. Byte write suspend allows system software to suspend a byte write to read data from any other lash memory array location.
I
64-Kbyte 64-Kbyte
Block Block
131 12
I I
64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block
81 7 61 5 4
t
'
64-Kbyte 64-Kbyte Hgure
Block Block Map
1 0
I
00000
3. Memory
2.'1 Data Protection
Depending on the application, the system designer may choose to make the V,, power supply switchable (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to VPPHIj2/s. The device accommodates either design practice and encourages optimization of the processor-memory interface. memory contents cannot be When Vp+VppLK, altered. The CUI, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to V,,. All write functions are disabled when Vcc is below the write lockout voltage VLKO or when RP# is at V,,. The device's block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations.
Rev. 1.0
LHFOSCH2
a
active power until the operatior
3 BUS OPERATION
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
consuming completes.
3.4
Deep Power-Down
mode.
RP# at V,, initiates the deep power-down
3.1
Read
In read modes, RP#-low deselects the memory places output drivers in a high-impedance state ant turns off all internal circuits. RP# must be held low foi a minimum of 100 ns. Time tPHQv is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, norma operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, ~;~low~rit~~ll o;botck;;; configuration modes, ' operation. RY/BY# remains low until the resei operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (VI,) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP's flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
Information can be read from any block, identifier codes, or status register independent of the V,, voltage. RP# can be at either V,, or V,,. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Four control pins dictate the data flow in and out of the component: CE#, OE#, WE#, and RP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQo-DQ,) control and when active drives the selected memory data onto the I/O bus. WE# must be at V,, and RP# must be at V,, or V,,. Figure 15 illustrates a read cycle.
3.2 Output
Disable
With OE# at a logic-high level (V,,), the device outputs are disabled. Output pins DQc-DQ, are 3laced in a high-impedance state.
3.3 Standby
ZE# at a logic-high level (V,,) places the device in standby mode which substantially reduces device lower consumption. DQc-DQ, outputs are placed in 3 high-impedance state independent of OE#. If deselected during block erase, byte write, or lock-bit :onfiguration, the device continues functioning, and
Rev. 1.0
LHF08CH2
9
5 Read Identifier
Codes Operation
3.6
Write
re read identifier codes operation outputs the anufacturer code, device code, block lock nfiguration codes for each block, and the master :k configuration code (see Figure 4). Using the anufacturer and device codes, the system CPU can rtomatically match the device with its proper gorithms. The block lock and master lock nfiguration codes identify locked and unlocked lcks and master lock-bit setting.
Writing commands to the CUI enable reading o device data and identifier codes. They also contra inspection and clearing of the status register. Wher VPP=VPPHt/2/3, the CUI additionally controls bloc1 erasure, byte write, and lock-bit configuration. The Block Erase command requires appropriatt command data and an address within the block to bc erased. The Byte Write command requires the command and address of the location to be written Set Master and Block Lock-Bit commands require the command and address within the device (Maste Lock) or block within the device (Block Lock) to bc locked. The Clear Block Lock-Bits command require: the command and address within the device. The CUI does not occupy an addressable memog location. It is written when WE# and CE# are active The address and data needed to execute a commanc are latched on the rising edge of WE# or CEf (whichever goes high first). Standard microprocessor write timings are used. Figures 16 and 17 illustrate WE# and CE#-controlled write operations.
FOO02 1 FOOOI FOOOO
Block 15 Lock Configuration Code Reserved for Future Implementation (Blocks 2 through 14)
4 COMMAND
DEFINITIONS
1FFFF
10004 10003 100021 10001
Reserved for Future Implementation
Read operation: When the V,, voltage I V,,,,, from the status register, identifier codes, or block: are enabled. Placing VPPHlIti3 on V,, enable: successful block erase, byte write and lock-bi configuration operations. 1 Device operations are selected by writing specific commands into the CUI. Table 4 defines the.% commands.
Block 1 Lock Configuration Code Reserved for Future Implementation . Reserved for Future Implementation
10000
OFFFF
Btock 1
00004 00003 00002 00001
Master Lock Configuration Code Block 0 Lock Configuration Code ______---____-----__~-------------~~~~ Device Code __-------_--------~--------~~~~~~~~~~ Manufacturer Code
`igure 4. Device Identifier
Code Memory
Map
Rev. 1.0
LHF08CH2
10
Mode Read Output Disable Standby Deep Power-Down Read Identifier Codes Write
Notes 1,2,3,8 3 3 4 8 3,6,7,8
RP# V$H or HH
`1,
Table 3. Bus Operations WE# CE# OE#
"IL "IL "I, "IL "I, "I, "I,
Address X X X X See Figure 4 X
Vpp X X X X X X
DQIL,
DOUT
RY/BY# X X X Vnl, `OH X
VHH
Or Or
High Z High Z High Z Note 5
DlN
viH
VHH V,,
vlH Or
X X
"IL "I,
X X
"I, "IL
X
"IL "IL
V# v$+ Or HH
UOTES: I. Refer to DC Characteristics. When VpprlC'3"I I Icz
1
1
Byte Write
(
Write BA OlH 2 7 Write BA 60H Set Block Lock-Bit Write X FlH Set Master Lock-Bit 2 7 Write X 60H Write X DOH 2 8 Write X 60H Clear Block Lock-Bits NOTES: 1. BUS operations are defined in Table 3. 2. X=Any valid address within the device. IA=ldentifier Code Address: see Figure 4. BA=Address within the block being erased or locked. WA=Address of memory location to be written. 3. SRD=Data read from status register. See Table 7 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID=Data read from identifier codes. 4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock codes. See Section 4.2 for read identifier code data. 5. If the block is locked, RP# must be at V,, to enable block erase or byte write operations. Attempts to issue a block erase or byte write to a locked block while RP# is VI,. 6. Either 40H or 10H are recognized by the WSM as the byte write setup. 7. If the master lock-bit is set, RP# must be at V,, to set a block lock-bit. RP# must be at V,, to set the master lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is VI,. 8. If the master lock-bit is set, RP# must be at V,, to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is V,,. 9. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
Rev. 1 .O
LHF08CH2
12
4.1 Read Array Command
Upon initial device power-up and after exit from deep oower-down mode, the device defaults to read array node. This operation is also initiated by writing the Read Array command. The device remains enabled `or reads until another command is written. Once the nternal WSM has started a block erase, byte write or ock-bit configuration, the device will not recognize :he Read Array command until the WSM completes ts operation unless the WSM is suspended via an Erase Suspend or Byte Write Suspend command. The Read Array command functions independently of :he V,, voltage and RP# can be V,, or V,,.
4.3
Read Status Register
Command
The status register may be read to determine when i block erase, byte write, or lock-bit configuration is complete and whether the operation completec successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations outpu' data from the status register until another valic command is written. The status register contents arc latched on the falling edge of OE# or CE#, whichevel occurs. OE# or CE# must toggle to V,, before further reads to update the status register latch. The Reac Status Register command functions independently o the V,, voltage. RP# can be V,, or V,,.
4.2 Read Identifier
Codes Command
4.4
Clear Status Register
Command
The identifier code operation is initiated by writing the qead Identifier Codes command. Following the :ommand write, read cycles from addresses shown in `igure 4 retrieve the manufacturer, device, block lock :onfiguration and master lock configuration codes see Table 5 for identifier code values). To terminate he operation, write another valid command. Like the ?ead Array command, the Read Identifier Codes :ommand functions independently of the V,, voltage %nd RP# can be V,, or V,,. Following the Read dentifier Codes command, the following information :an be read: Table 5. Ideni tifi ier Codes Code Manufacture Code Device Code Block Lock Configuration *Block is Unlocked *Block is Locked *Reserved for Future Use Master Lock Configuration @Device is Unlocked *Device is Locked *Reserved for Future Use 1 30TE: . X selects the specific block lock configuration code to be read. See Figure 4 for the device identifier code memory map.
Status register bits SR.5, SR.4, SR.3, and SR.l are set to "1 "s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 7). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurre during the sequence. To clear the status register, the Clear command (50H) is written. It functions of the applied V,, Voltage. RP# can This command is not functional during byte write suspend modes. Status Register independently be V,, or V,,. block erase or
4.5
Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase block data to FFH). Block changes all preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 5). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7.
Rev. 1.0
LHF08CH2
13
When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1 `I. Also, reliable block erasure can only occur when and vCC=vCC2/314 v,,=v PPi+l2/3* In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while Vpp&,,,k, SR.3 and SR.5 will be set to "1". Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that RP#=V,,. If block erase is attempted when the corresponding block lock-bit is set and RP#=V,,, SR.l and SR.5 will be set to "1". Block erase operations with V,,cRP#cVH, produce spurious results and should not be attempted.
corresponding block lock-bit be cleared or, if set, tha RP#=V,,. If byte write is attempted when the corresponding block lock-bit is set and RP#=V,, SR.1 and SR.4 will be set to "1". Byte write operations with V,,cRP#cVHH produce spurious results and should not be attempted.
4.7
Block Erase Suspend
Command
The Block Erase Suspend command allows block-erase interruption to read or byte-write data ir another block of memory. Once the block-erase process starts, writing the Block Erase Suspenc command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend commanc is written. Polling status register bits SR.7 and SR.E can determine when the block erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to V,,. Specification twHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Byte Write Suspend command (see Section 4.8), a byte write operation can also be suspended. During a byte write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/BY# output will transition to V,,. However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 7). V,, must remain at V,PH1,2,3 (the same V,, level used for block erase) while block erase is suspended. RP# must also remain at V,, or V,, (the same RP# level used for block erase). Block erase cannot resume until byte write operations initiated during block erase suspend have completed.
4.6 Byte Write Command
Byte write is executed by a two-cycle command sequence. Byte write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the -ising edge of WE#). The WSM then takes over, controlling the byte write and write verify algorithms nternally. After the byte write sequence is written, the device automatically outputs status register data Nhen read (see Figure 6). The CPU can detect the zompletion of the byte write event by analyzing the ?Y/BY# pin or status register bit SR.7. Nhen byte write is complete, status register bit SR.4 should be checked. If byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1 "s that do not juccessfully write to "0"s. The CUI remains in read status register mode until it receives another :ommand. qeliable byte writes can only occur when Jcc=Vcc2/3,4 and VPrz~VPPr+t/2/3. In the absence of his high voltage, memory contents are protected against byte writes. If byte write is attempted while /+V,,,,, status register bits SR.3 and SR.4 will be ret to "1 `I. Successful byte write requires that the
Rev.
1.0
LHF08CH2
14
4.8
Byte Write Suspend
Command
the RP# pin. See Table 6 for a summary and software write protection options.
of hardwar'
1
The Byte Write Suspend command allows byte write interruption to read data in other flash memory locations. Once the byte write process starts, writing the Byte Write Suspend command requests that the WSM suspend the byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Byte Write Suspend command is written. Polling status register bits SR.7 and SFi.2 can determine when the byte write operation has been suspended (both will be set to "1"). RY/BY# will also transition to VOH. Specification tWHRHl defines the byte write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while byte write is suspended are Read Status Register and Byte Write Resume. After Byte Write Resume command is written to the flash memory, the WSM will continue the byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to V,,. After the Byte Write Resume command is written, the device automatically outputs status register data when read (see Figure 8). V,, must remain at VPPH1,2,3 (the same V,, level used for byte write) while in byte write suspend mode. RP# must also remain at V,, or V,, (the same RP# level used for byte write).
Set block lock-bit and master lock-bit are executed b a two-cycle command sequence. The set block c master lock-bit setup along with appropriate block c device address is written followed by either the SE block lock-bit confirm (and an address within thl block to be locked) or the set master lock-bit confirr (and any device address). The WSM then control the set lock-bit algorithm. After the sequence i written, the device automatically outputs statu register data when read (see Figure 9). The CPU car detect the completion of the set lock-bit event b analyzing the RY/BY# pin output or status register bi SR.7. When the set lock-bit operation is complete, statu: register bit SR.4 should be checked. If an error i: detected, the status register should be cleared. The CUI will remain in read status register mode until : new command is issued. This two-step sequence of set-up followed b! execution ensures that lock-bits are not accidentall! set. An invalid Set Block or Master Lock-B/ command will result in status register bits SR.4 ant SR.5 being set to "1". Also, reliable operations occu only when Vcc=Vcc2,3,4 and VPP=VPPH,,2,3. In tht absence of this high voltage, lock-bit contents arc protected against alteration. A successful set block lock-bit operation requires tha the master lock-bit be cleared or, if the maste lock-bit is set, that RP#=V,,. If it is attempted wit1 the master lock-bit set and RP#=V,,, SR.l and SR.l will be set to "1" and the operation will fail. Set block lock-bit operations while VIH4.9 Set Block and Master Lock-Bit Commands
4 flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. The block lock-bits gate program and erase operations while the master lock-bit gates 3lock-lock bit modification. With the master lock-bit lot set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Master -ock-Bit command, in conjunction with RP#=V,,, jets the master lock-bit. After the master lock-bit is jet, subsequent setting of block lock-bits requires 10th the Set Block Lock-Bit command and V,, on
Rev. 1.0
LHF08CH2
15
l.10
Clear Block Lock-Bits
Command
411set block lock-bits are cleared in parallel via the Zlear Block Lock-Bits command. With the master ock-bit not set, block lock-bits can be cleared using )nly the Clear Block Lock-Bits command. If the naster lock-bit is set, clearing block lock-bits requires 10th the Clear Block Lock-Bits command and V,, on he RP# pin. See Table 6 for a summary of hardware md software write protection options. Zlear block lock-bits operation is executed by a wo-cycle command sequence. A clear block lock-bits setup is first written. After the command is written, the device automatically outputs status register data vhen read (see Figure 10). The CPU can detect :ompletion of the clear block lock-bits event by analyzing the RYIBY# Pin output or status register bit SR.7. Yhen the operation is complete, status register bit jR.5 should be checked. If a clear block lock-bit error s detected, the status register should be cleared. `he CUI will remain in read status register mode until nother command is issued.
This two-step sequence of set-up followed b\ execution ensures that block lock-bits are no accidentally cleared. An invalid Clear Block Lock-Bit: command sequence will result in status register bit: SR.4 and SR.5 being set to "1". Also, a reliable clea block lock-bits operation can only occur wher Vcc=Vcc2/3,4 and VPP=VPPHI12/s. If a clear bloc1 lock-bits operation is attempted while V,,rV,,,, SR.3 and SR.5 will be set to "1". In the absence o this high voltage, the block lock-bits content arc protected against alteration. A successful clear bloc1 lock-bits operation requires that the master lock-bit i: not set or, if the master lock-bit is set, that RP#=V,, If it is attempted with the master lock-bit set ant RP#=V,,, SR.1 and SR.5 will be set to "1" and the operation will fail. A clear block lock-bits operatior with V,,cRP#cV,, p reduce spurious results ant should not be attempted. If a clear block lock-bits operation is aborted due tc V,, or Vc, transitioning out of valid range or RP# active transition, block lock-bit values are left in ar undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents tc known values. Once the master lock-bit is set, ii cannot be cleared.
Operation Block Erase or Byte Write
1 Master 1 Lock-Bit X
Set Block Lock-Bit Set Master Lock-Bit Clear Block Lock-Bits 1
0 1 X 0 1
Table 6. Write Protection Alternatives 1 Block 1 1L Effect Block Erase and Byte Write Enabled Block is Locked. Block Erase and Byte Write Disabled 1 Block Lock-Bit Override. Block Erase and Bvte Write I \I "HH Enabled X VI,, or VWH Set Block Lock-Bit Enabled X V,H Master Lock-Bit is Set. Set Block Lock-Bit Disabled VHH 1 Master Lock-Bit Override. Set Block Lock-Bit Ena bled 1 X V,H 1 Set Master Lock-Bit Disabled V Set Master Lock-Bit Enabled X V 0rV Clear Block Lock-Bits Enabled X V Master Lock-Bit is Set. Clear Block Lock-Bits Disabled Master Lock-Bit Override. Clear Block Lock-Bits \I "HH 1 Enabled
B
Rev. 1 .O
SHARP
LHF08CH2
WSMS 7
/
ESS 6
1
ECLBS 5
Table 7. Status 1 BWSLBS 4
Register Definition 1 VPPS 1 BWSS 3 NOTES: 2
1
DPS 1
R 0
SR.7 = WRITE 1 = Ready 0 = Busy
STATE MACHINE
STATUS
Check RY/BY# or SR.7 to determine block erase, byte write, or lock-bit configuration completion. SR.6-0 are invalid while SR.7="0". If both SR.5 and SR.4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of V,, level. The WSM interrogates and indicates the V,, level only after Block Erase, Byte Write, Set Block/Master Lock-Bit, or Clear Block Lock-Bits command sequences. SR.3 is not guaranteed to reports accurate feedback only when V,,#V,,,,,~,,. SR.l does not provide a continuous indication of master and block lock-bit values. The WSM interrogates the master lock-bit, block lock-bit, and RP# only after Block Erase, Byte Write, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or RP# is not V,,. Reading the block lock and master lock configuration codes after writing the Read Identifier Codes command indicates master and block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register.
SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR LOCK-BITS STATUS 1 = Error in Block Erasure or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits SR.4 = BYTE WRITE AND SET LOCK-BIT STATUS 1 = Error in Byte Write or Set Master/Block Lock-Bit 0 = Successful Byte Write or Set Master/Block Lock-Bit SR.3 = V,, STATUS 1 = V,, Low Detect, Operation O=V,,OK Abort
SR.2 = BYTE WRITE SUSPEND STATUS 1 = Byte Write Suspended 0 = Byte Write in Progress/Completed SR.l = DEVICE PROTECT STATUS 1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
LHF08CH2
Command I / write 1 EraseSetup 1 Data=20H Addr=Wlthin Data-DOH Addr=Withm
Comments
Block to be Erased
write
Block to be Erased
Read
Status Rqster
Data
Standby
Check SR.7 ,=WSM Ready O=WSM Busy
Full status check can be done after each block erase or after a sequence block erasures. Wnte FFH after the last operation to place device in read array mode.
of
Check if Desired
FULLSTATUSCHECKPROCEDURE BUS Command Comments
Operation
Standby
Check SR.3 l=Vpp Error Detect Check SR. 1 l=Device Protect Detect RP#=V,,+Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4,5 Both t=Command
Standby
Sequence
Error
Check SR.5 l=Block Erase Error ;R.5,SR.4.SR.3 and SR., are only cleared by the Clear Status Register Command in casas where multiple blocks are erased before full status is checked. error is detected. clear the Status Register before attempting retry or other error recovery. Block Erase Error
Block Erase Successful
Figure 5. Automated
Block
Erase Flowchart
Rev. 1.0
SHARI=
LHF08CH2 18
Command
Comments
write
Setup Byte Write
DatedOH AddkLwabon
to Be Wlitten
Wnte
Byte Wnte
Data=Data to Be Written Addr=Lccation to Be Written
Read
Status Register
Data
Suspend Byte write Loop
Standby
Check SR.7 l=WSM Ready O=WSM Busy
Repeat for subsequent byte writes. SR full status check can be done after each byte write. or after a sequence byte writes. Wnte FFH after the last byte write operation to place device III read array mode.
of
FULL STATUS
CHECK
PROCEDURE
Command
Comments
Standby
Check SR.3 1+,x Error Detect Check SR. 1 l=Devse Protect Detect RP#=VIH,Block Lock-Bit is Set Only required for systems Implementing lock-btt configuration Check SR.4 l=Data Wnte Error
Standby
Device
Protect Error Standby
57.4.SR.3 and SR. 7 are only cleared by the Clear Status Regtster command in cases where multiple locations are written before full status is checked. I f error is detected, clear the Status Register before attempting retry or other error reco"ely.
Byte Wnte Successful
Figure 6. Automated
Byte Write Flowchart
Rev. 1 .O
LHF08CH2
start
Bus Operation
Command I
Comments I
Write BOH
Status Register
Check 533.7 1 =WSM Reacty o=WSM Busy Check SR.6 l=Block Erase Suspended O=Block Erase Completed El-&% Resume Data=DOH Addr=X
write
Figure 7. Block
Erase Suspend/Resume
Flowchart
Rev. 1.0
LHF08CH2
r
Bus Operation Command I Byte Write Suspend Data=BOH Addr=X
write
Read
status Data Regster
Addr=X Check SR.7 1 =WSM Ready O=WSM Busy Check SR.2 l=Byte Write Suspended o=Byte Write Completed Data=FFH Addr=X
standby
SR.7= 1
0 standby
i:t
Read Army
Figure 8. Byte Write Suspend/Resume
Flowchart
Rev. 1.0
SHARP
LHF08CH2 21
Bus Operation
Command
Commenb
write
set Block/Master Lock-Bit Sehrp set
Data=6OH Addr=Block Address(Block), Dewca Address(Master) Data=OlH(Block), FlH(Master) Addr=Blcck Address(Block), Device Address(Master)
Write OIHIFIH, write Lock-Bit
Block or Master Confirm
Read
Status Register
Data
Standby
Check SR.7 l=WSM Ready O=WSM Busy
Check If Desired
Repeat for subsequent lock-bit set operations. Full status check can be done after each lock-btt set oper'dtion or after a sequence of lock-bit set operations. Wnte FFH after the last lock-bit set operation to place device I" read army mode.
FULL STATUS
CHECK
PROCEDURE BUS Operation
Read Status Register Data(See Above)
Command
Comment3
Standby
Check SR.3 t=VpP Error Detect Check SR.1 I=Dewce Protect Detect RP#+, (Set Master Lock-Blt Operation) RP#=VIH, Master Lock-Bit is Set (Set Block Lock-Blt Operation) Check SR.4,5 Both l=Command Sequence Error Check SR.4 l=Set Lock-Bit
Standby
Device
Protect Error
Standby
Standby
Error
Set Lock-Bit
Error
SR.5.SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register command I" cases where multiple lock-bits are set before full status is checked. If error IS detected, clear the Status Register before attempting retry or other error recovery.
Set Lock-Bit
Successful
Figure 9. Set Block
and Master
Lock-Bit
Flowchart
Rev. 1.0
LHF08CH2
22
Start
BUS Operation
Command
Comments
x
write 60H
WI-Its
Clear Block Lock-Bits Setup Clear Block Lock-Bits Confirm
Data=M)H Addr=X Data=DOH Addr=X
Write
Read
Status Register
Data
Standby
Check SA.7 l=WSM Ready O=WSM Busy operation to
SR.7= 1
0
\ Nrite FFH after the Clear Block Lock-Bits Fhate device in read array mode.
+
Check If Desired
FULL STATUS
CHECK
PROCEDURE BUS Operation
Command
Comments
Standby
Check SR.3 l=Vpp Error Detect Check SR. 1 MJevice Pmtect Detect RP#=V,H, Master Lock-Bit Check SR.4,5 Both l=Command Sequence Error Check SR.5 l&tear Block Lock-Bits
Standby
is Set
Device
Protect Error
Standby
Standby
Error
SR.5.SR.4.SR.3 and SR. 1 are only cleared by the Clear Status Register command. f error is detected, clear the Status Register before attempting retry or other error recovery.
Figure
10. Clear Block
Lock-Bits
Flowchart
Rev. 1.0
LHFOSCH2
23
1
5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control
RY/BY# is also VOH when the device is in block eras suspend (with byte write inactive), byte write suspenc or deep power-down modes.
The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention not occur.
5.3
Power Supply Decoupling
will
To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
Flash memory power switching characteristics require careful device decoupling. System designers arc interested in three supply current issues; standb current levels, active current levels and transien peaks produced by falling and rising edges of CEI and OE#. Transient current magnitudes depend OI the device outputs' capacitive and inductive loading Two-line control and proper decoupling capacito selection will suppress transient voltage peaks. Eacl device should have a 0.1 uF ceramic capacito connected between its Voo and GND and between it: V,, and GND. These high-frequency, low inductance capacitors should be placed as close as possible tc package leads. Additionally, for every eight devices a 4.7 uF electrolytic capacitor should be placed at the array's power supply connection between V,, ant GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance.
5.2 RY/BY# and Block Erase, Byte Write, and Lock-Bit Configuration Polling
RY/BY# is a full CMOS output that provides a lardware method of detecting block erase, byte write snd lock-bit configuration completion. It transitions ow after block erase, byte write, or lock-bit :onfiguration commands and returns to V,, when he WSM has finished executing the internal algorithm. 3Y/BY# can be connected to an interrupt input of the ;yStf?m CPU or controller. It is active at all times.
5.4
Vpp Trace on Printed Circuit
Boards
Updating flash memories that reside in the targe system requires that the printed circuit boarc designer pay attention to the V,, Power supply trace The V,, pin supplies the memory cell current for by& writing and block erasing. Use similar trace width: and layout considerations given to the Voc powel bus. Adequate V,, supply traces and decoupling wil decrease V,, voltage spikes and overshoots.
Rev. 1.0
LHF08CH2
24
5.5 Vcc, Vpp, RP# Transitions
Block erase, byte write and lock-bit configuration are not guaranteed if V,n falls outside of a valid V,,,,,,, range, Vcc falls outside of a valid Vcc2,3,4 range, or RP#&,,, or V,,. If V,, error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to V,, during block erase, byte write, or lock-bit configuration, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored. Device power-off or RP# transitions to V,, clear the status register. The CUI latches commands issued by system software and is not altered by V,, or CE# transitions or WSM actions. Its state is read array mode upon sower-up, after exit from deep power-down or after Vcc transitions below VLKO. After 3ven nust Array array block erase, byte write, or lock-bit configuration, after V,, transitions down to VpPLK, the CUI be placed in read array mode via the Read command if subsequent access to the memory is desired.
supply (V,, or Vcc) powers-up first. Internal circuitr resets the CUI to read array mode at power-up.
1
A system designer must guard against spuriou: writes for Vcc voltages above VLKO when V,, i! active. Since both WE# and CE# must be low for i command write, driving either to VI, will inhibit writes The CUl's two-step command sequence architecturt provides added level of protection against datr alteration. In-system block lock and unlock capability prevent: inadvertent data alteration. The device is disablec while RP#=V,, regardless of its control inputs state. '
5.7
Power Dissipation
When designing portable systems, designers mus consider battery power consumption not only durin! device operation, but also for data retention during system idle time. Flash memory's nonvolatilih increases usable battery life because data is retainec when system power is removed. In addition, deep power-down mode ensure: extremely low power consumption even when systen power is applied. For example, portable computing products and other power sensitive applications tha use an array of devices for solid-state storage car consume negligible power by lowering RP# to VI, standby or sleep modes. If access is again needed the devices can be read following the tpHav ant tPHWL wake-up cycles required after RP# is firs raised to V,,. See AC CharacteristicsRead Only and Write Operations and Figures 15, 16 and 17 fol more information.
5.6 Power-Up/Down
Protection
protection against writing, or lock-bit transitions. Upon as to which power
The device is designed to offer 3ccidental block erasure, byte :onfiguration during power lower-up, the device is indifferent
Rev. 1.0
LHF08CH2
25
6 ELECTRICAL 6.1 Absolute
SPECIFICATIONS Maximum Ratings*
Operating Temperature During Read, Block Erase, Byte Write and Lock-Bit Configuration . . .. . .. .. ..O"C to +7O"C(1) Temperature under Bias . . . .. . .. . .. .. . . -10C to +8O"C Storage Temperature . . .. . .. . .. .. . . .. . .. . .. .. -65C to +125"C
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation "Operating Conditions " is not beyond the recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES: 1. Operating temperature is for commercial temperature product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on V,, and V,, pins. During transitions, this level may undershoot to -2.OV for Maximum DC voltage on periods <20ns. input/output pins and Voc is Vcc+O.SI which, during transitions, may overshoot to Vcc+2.OV for periods c20ns. 3. Maximum DC voltage on V,, and RP# may overshoot to +14.OV for periods <20ns. 4. Output shorted for no more than one second. No more than one output shorted at a time.
Voltage On Any Pin (except Vcc, VP,, and RP#) . . .._..-2.OV to +7.OV@) V,, Supply Voltage . . .. .. . . . .. .. . .. . .. .. . . .. . -2.ov to +7.0@)
V,, Update Voltage during Block Erase, Byte Write and Lock-Bit Configuration .. .. .. .. . .. -2.OV to +14.OV(2J) RP# Voltage with Respect to GND during Lock-Bit Configuration Operations .. .. . . -2.OV to +14.0V(2J) Output Short Circuit Current . . .. .. . . .. . .. . .. .. . .. .. . 1 00mAc4)
6.2
Operating
Conditions
Temperature and Vcc Operating Conditions Symbol 1 Parameter 1 Notes Min. 1 Max. 1 Unit 1 Test Condition T, ( Operating Temperature 1 +70 I "C I Ambient Temperature 0 Van, Vcc Supply Voltage (2.7V-3.6V) 1 2.7 3.6 V Vr-c, Vnn Supply Voltage (3.3V+O.3V) V 3.0 3.6 Voo2 Vnr. Supply Voltage (5V+O.25V) 4.75 5.25 V V,, Vnn Supply Voltage (5V+O5V) 5.50 V 4.50 NOTE: 1. Block erase, byte write and lock-bit configuration operations with Vo,<3.OV should not be attempted. 6.2.1 CAPACITANCE(`) T,=+25"C, Typ. 6 8 f=l MHz Max. 8 12
Symbol C,N Ca,T NOTE: 1. Sampled,
Parameter Input Capacitance Output Capacitance not 100% tested.
Unit pF pF
Condition v,,=o.ov v(-y ,J-=O.OV
Rev. 1.11
LHF08CH2
1.2.2 AC INPUT/OUTPUT
TEST CONDITIONS
1:; -T--,j(Z2~+--Y
AC test inputs are driven at 2.7V for a Logic "1" and O.OV for a Logic Input rise and fall times (10% to 90%) Figure 11. Transient
Input/Output
Reference
Waveform
for Vcc=2.7V-3.6V
~~~~;~~~
AC test inputs are driven at 3.OV for a Logic "1" and O.OV for a Logic Input rise and fall times (10% to 90%) Figure 12. Transient
Input/Output Reference Waveform for VcC=3.3V*0.3V (High Speed Testing Configuration)
and VcC=5V+0.25V
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and V~L (0.45 V~L) for a Logic "0." Input timing begins (2.0 VmL) and VIL (0.8 V&. Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) ~10 ns.
at VIH
Figure 13. Transient
Input/Output Reference Waveform (Standard Testing Configuration)
for Vcc=SV*O.SV
Test Confi 1
uration
Ca acitance
Loadin
Value
DEVICE UNDER TEST CL Includes Jig Capacitance
0
OUT
Figure
14. Transient Equivalent Load Circuit
Testing
Rev. 1.2
LHF08CH2
27
L2.3 DC CHARACTERISTICS DC Ch - racteristics al Vcc=2.7V Vcr Typ. 1 Max. Lre, I kO.5 kO.5 * 20 0.1
I
Sym. `Li
`LO
Parameter Input Load Current Output Leakage V,, Current
Votes 1 1 1,3,6
Uni IJA CIA
`cc,
Standby Current
100 2
20
0.2
=lx
100 25 12 17 18
I
100
IJA
mA PA Vcc=VccMax. CE#=RP#=V,,., RP#=GND*0.2V b, ,,(RY/BY#)=OmA CMOS Inputs Vcc=VCCMax. CE#=GND f=5MHz(3.3V, 2.7V), 8MHz(5V) In, ,T=OmA TTL Inputs V,,=V,,Max. CE#=GND f=5MHz(3.3V, 2.7V), 8MHz(5V) In, ,T=OmA vDo=3.3v*o.3V
CCD CCR
Vcc Deep Power-Down Current dcc Read Current
1 133
ccw
ticc Byte Write or Set Lock-Bit Current
I,7
CCE
:cws lxxs. `PS TEL...`PD `PW
dcc Block Erase or 1,7 Zlear Block Lock-Bits Zurrent I,, Byte Write or Block v--irase Suspend Current Ipp Standby or Read hrrent I,, Deep Power-Down hrrent fpp Byte Write or Set ~ .ock-Bit Current Ipp Block Erase or Zlear Lock-Bit Current Ipp Byte Write or Block :rase Suspend Current
-s
7 7 18 8 1 _+2 10 *15 200 5 -' 10 A2 10 0.1 0.1
l-l20
I
35
mA
50
mA
17
I
-
I
-
mA mA mA mA mA mA mA
6
1
1
1 10
CE#=V,,, vpp_Vcc. RP#=GND*0.2V Vpp=3.3V~0.3V dpp=5.0V+0.5V Vpp=12.0V+0.6V vpp=3.3v~o.3v vpp=5.0v+o.5v VP,=1 2.OV&O.6V
& CIA IJA
40 40 15 20 20 15 200 _ 40 15 20 15 200 mA mA mA mA mA mA
`PE
-
`PWS 9xS-
10
Rev. 1.2
SHARP
LHFOBCH2 28
Sym. V,,
4,
Parameter Input Low Voltage Input High Voltage Output Low Voltage
Notes 7 7 3,7
Continued DCC :h ,aracteristics &-.& =; !.7V Vcc=3.3V 1 Vc.,dV Min. Max. Min. Max. Min. Max. -0.5 0.8 -0.5 0.8 -0.5 0.8 Vcc VCC 2.0 +0.5 2.0 vcc 2.0 +0.5 +0.5 0.45
Unit V V
Test Conditions
VOL
V
I
VoHl
Output High Voltage V-J Output High Voltage (CMOS)
3,7 2.4
I I I
V 1 0.85 1 0.85
Vcc=VccMin. IO ,=5.8mA(Vcc=5V), loL=2.0mA (Vnn=3.3V, 2.7V) Vcc=VcoMin. loH=-2.%lA(vCc=5v), lo,=-2.0mA(vcc=3.3v) In,,=-1 .5mA(Vr.,=2.7V)
VOH2
3,7
0.85 Yc.cL vcc -0.4
V V 1.5 V V In!+=-1 OOuA
V,,r+ Lock-Bit Operations V,, during Byte Write, Block Erase or Lock-Bit Operations V,, during Byte Write, Block Erase or Lock-Bit Operations Vcr: Lockout Voltage f?P# Unlock Voltage
-
-
5.5
V
V,,Hs
2.0 8,9 j 11.4 / 12.6 / 11.4
12.6
V V
V, kr,
vHH
12.6
V
Set master lock-bit Override master and block lock-bit
IOTES: . All currents are in RMS unless otherwise noted. Typical values at nominal Voc voltage and T,=+25"C. These currents are valid for all product versions (packages and speeds). If read or byte written while in erase suspend mode, . `CCWS and `CCES are specified with the device de-selected. the device's current draw is the sum of lccws or IocEs and lCCR or I,,,, respectively. `. Includes RY/BY#. . Block erases, byte writes, and lock-bit configurations are inhibited when V&J,,,,, and not guaranteed in the range between VppLk(max.) and VppHt(min.), between Vnr+n(max.) and Vpp&min.), between Vpp&max.) and VppHs(min.), and above VppHs(max.). . Automatic Power Savings (APS) reduces typical I,,, to 1mA at 5V Vcc and 3mA at 2.7V and 3.3V Voc in static operation. . CMOS inputs are either Vco- +0.2V or GNDk0.2V. TTL inputs are either V,, or Vi,. . Sampled, not 100% tested. . Master lock-bit set operations are inhibited when RP#=V,,. Block lock-bit configuration operations are inhibited when the master lock-bit is set and RP#=VrH. Block erases and byte writes are inhibited when the corresponding block-lock bit is set and RP#=VrH. Block erase, byte write, and lock-bit configuration operations are not guaranteed with Vcc <3.OV or VrHRev. 1.2
LHFOSCH2
29
6.2.4
I
AC CHARACTERISTICS
- READ-ONLY
OPERATIONS(`) T,pO"C to +7O"C 1 Notes 1 LH28F008SGL150 Max. Min. .-1 Unit 1 11
Vc,,=2.7V-3.6V,
Sym.
1
Versiond4) Parameter
tr,, nx GHC)7 LH
OE# to Outr OE# High to Output in High Z Output Hold from Address, CE# ot Whichever Occurs First Read-Only Operations for notes 1 through 4. Vc:,=3.3V+0.3V, Versiond4) Parameter Read Cyc& Time Addre: 1RP# Hiqh to Output Delay
3
0
ns
NOTE: See 5.OV V,,
Tg -0C to +7O"C 1 Notes
. ..------SC-L,20 LH28FO08
Sym. tJ"A" ta"n" tF, (-Jv tpwnv t
Min. 120
Max.
Unit ns ns
NOTE: See 5.OV V,,
Read-Only Operations for notes 1 through 4.
Rev. 1.0
SI-IARP
LHF08CH2 30
Vcc=5Vdl.5V, 5VkO.25V, Vcc=5V+0.25Vj Sym. t*"n" t*"n" tpHn"
T,=O"C to +70X LH28FO08Sc-L=(5)
1 I
k, nx
Read Cycle Address to C CE# to Outp RP# High to OE# to Outp CE# to Outp CE# High to VUhc/UL ,,, OE#to Output in Low Z Output Hold from Address, Change, Whichever Occurs
NOTES: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to tELQV-tGLQv after the falling edge of CE# without impact on tELQv. 3. Sampled, not 100% tested. 4. See Ordering Information for device speeds (valid operational combinations). 5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed Configuration) for testing characteristics. 6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics.
Rev. 1.11
SHARP
LHF08CH2 31
Device Address Selection t Address r Stable
Data Valid
.I.,....,,
VIH
CE#(E)
VIL c
VIH
OE#(G) WL
VIH WE#(W)
VIL tOH,--+ VOH ,1,,,,,,,,
DATA(D/Q) (DQo-DQ7)
VOL
vcc
VIH RP#(P)
VIL
Figure
15. AC Waveform
for Read Operations
L Rev. 1.0
SHARP
LHF08CH2 32
6.2.5
AC CHARACTERISTICS
- WRITE OPERAATION Vc.=2.7V-3.6V, Versiond5) Parameter TA=O"C to +7O"C Notes 2 LH28F008SGL150 Min. 1 Max. 150 1 Unit ns IJS
tA"A"
tPl-!Wl
Write Cycle Time RP# High Recovery
to WE# Going Low
NOTE: See 5.OV V,,
WE#-Controlled
Writes for notes 1 through 5. Vcc=3.3V+0.3V, Versiond5) Parameter T`,=O"C to +70X 1 Notes 2 1 LH28F008SC-L120 Min. Max. 120 1 0 70 100 100 50 50 5 5 0 25 100 0 0 0 Unit --..ns p3
Svm. t d\,A\l tpuw, fF, w,
tWl WH
& tvpWCl t*,,-,,,,,, tnvw,, twwnx
tWHAX
tWHFH bacHw, twHR, bur,, tn"v, tn"pH IOTE: ;ee 5V V,,
I 1Write Cvcle Time RP# High Recovery tcI WE# Going Low CE# Setup to WE# Going Low WE#P- ulse Width -~~ 1RP# VHH Setup to WE# Going High 1Vpp Setup to WE!# Going High [ Address Setup to WE # Going High [ Data Setup to WE# G oing High 1 Data Hold fron I WE# High ) Address Hold From WE# Hiah CE# Hold from VVE# High WE# Pulse Width I High WE# High to RY/ BY# Going Low Write Recovery before Read Vpp Hold from Valid SRD, RY/BY# High RP# V,,,, Hold from Valid SRD, RY/BY# High AC Characteristics - Write Operations
2 2 3 3
2,4 2,4
ns "C I._ ns ns ns ns ns nc I *u ns ns ns ns ns ns
for Notes 1 through 5.
Rev. 1.2
LHFOSCH2
UOTES: I. Read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as during read-onry operations. Refer to AC Characteristics for read-only operations. !. Sampled, not 100% tested. 3. Refer to Table 4 for valid A,, and D,, for block erase, byte write, or lock-bit configuration. 1. V,, should be held at VPPH1,2,3 ( and if necessary RP# should be held at V,,) until determination of block erase, byte write, or lock-bit configuration success (SR.1/3/4/5=0). 5. See Ordering Information for device speeds (valid operational combinations). 5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration) for testing characteristics. 7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics.
Rev. 1.2
SHARP
LHFOBCH2
1 rcs----VIH
2
3
4
5
6
ADDRESSES(A)
CE#(E)
tWHGL
VIH
OE#(G)
VIL VIH
WE#(W)
VIL VIH
DATA( D/Q)
VOH
RY/BY#(R)
RP#(P)
NOTES: 1. Vcc power-up 2. Write block 3. Write block 4. Automated 5. Read status 6. Write Read
and standby. erase or byte write setup. erase confirm or valid address erase or program delay. register data. Array command.
and data.
Figure
16. AC Waveform
for WE#-Controlled
Write Operations
Rev. 1 .O
LHF08CH2
35
6.2.6
ALTERNATIVE
CE#-CONTROLLED
WRITES(`) Vc:,=2.7V-3.6V, T,=O"C to +7O"C 1 Notes 2 LH28F008SGL150 Min. Max. 150 1 0 70 50 50 5 5 0 25 f-l " Unit
Versiond5) Parameter
See 5.OV V,,
Alternative CE#-Controlled
Writes for notes 1 through 5. T,=O"C
EE
3 3
I
ns ns
Sym. t*"n" tp&p, tw, F, tp, FH t
Vbc=3.3V+0.3V, Versiond5) Parameater . .a.-...---. Write RP# WE# CE# RP# Cycle Time High Recovery to CE# : Going Low Setup to CE# uullly p-`-LOW ' Pulse Width V,, Setup to Ccw
to +70X I 2 3 LH28F008SC-L120 Min. Max.
.--
Unit
p.S
i---c--
1 0 -7n
I
t
ns nc ns
I I.2
tfq&, CE# Pulse Width High CE# High to RY/BY# Going Low tp)+q ffzHr,, Write Recovery before Read Vpp Hold from Valid SRD, RY/BY# High 2,4 hNl 2,4 w?OVPH RP# VHH Hold from Valid SRD, RY/BY# High NOTE: See 5V Vc, Alternative CE#-Controlled Writes for Notes 1 through 5.
25 100 0 0 0
ns ns ns ns ns
Rev. 1.0
LHF08CH2
etuo to Cl
7" -!
40 5 5 0 9r;
II>
ns ns ns ns -A
NOTES: 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. 3. Refer to Table 4 for valid A,, and DIN for block erase, byte write, or lock-bit config.uration. 4. V,, should be held at VPPHl12,s ( and if necessary RP# should be held at V,,) until determination of block erase byte write, or lock-bit configuration success (SR.1/3/4/5=0). 5. See Ordering Information for device speeds (valid operational combinations). 6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration) for testing characteristics. 7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics.
Rev. 1 .ll
LHF08CH2
37
A---VIH
1
2
3
4
5
A
ADDRESSES(A)
VIL VIH
WE#(W)
VIL
OE#(G)
VIH
CE#(E)
VIL VIH
DATA( D/Q)
VIL VOH
RY/BY#(R)
VOL J VHH
RP#(P)
VIH VIL -
NOTES: 1. Vcc power-up 2. Write block 3. Write block 4. Automated 5. Read status 6. Write Read
and standby. erase or byte write setup. erase confirm or valid address erase or program delay. register data. Array command.
and data.
Figure
17. AC Waveform
for CE#-Controlled
Write Operations
Rev. 1.0
SHARP
LHF08CH2
2.7 RESET OPERATIONS
VOH
RY/BY#(R)
VOL VIH
FlP#(P)
VIL
(A)Reset
VOH
During
Read Array
Mode
RY/BY#(R)
VOL p VIH tPLAH
RP#(P)
VIL
(B)Reset 2.7Vi3.3Vi5V vcc
ML
During
Block L
Erase,
Byte Write,
or Lock-Bit
Configuretion
VIH
b35VPH
-
RP#(P)
VIL
I
7-
(C)RP#
rising
Timing
Figure 18. AC Waveform
for Reset Operation
Sym.
`LPH
`LRH
35VPH
Parameter RP# Pulse Low Time (If RP# is tied to Vcc, this specification is not applicable) RP# Low to Reset during Block Erase, Byte Write or Lock-Bit Configuration V,, 2.7V to RP# High V,, 3.OV to RP# High Vco 4.5V to RP# High
Reset AC Specifications(`) Vr.,=2.7V Notes Min. Max. 100 -
Vn,=3.3V Max. Min. 100 20
V~+iV Min. Max. 100 12
Unit ns
2,3
P ns
4
100
100
100
ITES: These specifications are valid for all product versions (packages and speeds). If RP# is asserted while a block erase, byte write, or lock-bit configuration operation is not executing, the reset will complete within 1OOns. A reset time, tPHQV, is required from the latter of RY/BY# or RP# going high until outputs are valid. When the device power-up, holding RP# low minimum 1OOnsis required after Vcc has been in predefined range and also has been in stable there.
Rev. 1.0
LHF08CH2
6.2.8
BLOCK
ERASE,
BYTE WRITE AND LOCK-BIT
CONFIGURATION
PERFORMANCE(3~4~5)
:wHQv4
FHOVA
Clear Block Lock-Bits Byte Write Suspend Read Erase Suspend
Time Latency Time to
2
1.1 5.6 9.4
5 7 13.1
1 5.2 9.8
4 7.5 12.6
S
tWHRH, tF,,RH, )"HnHz
FHRH7
P IJS
Latency Time to Read
NOTES: 1. Typical values measured at TA=+25"C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled but not 100% tested. 5. Block erase, byte write and lock-bit configuration operations with Vccc3.OV and/or VPP<3.0V are not guaranteed.
Rev. 1.3
SHARP
LHF08CH2
ADDITIONAL 1 Ordering
INFORMATION Information
Product line designator for all SHARP Flash products I I I
~L~H12/81F~O~018/SICi(H~RlDevice Density 008 = 8-Mbit Architecture S = Regular Block Power Supply Type C = SmartVoltage Technology
lLl815j w
F
Access Speed (ns) 85:85ns(5V,30pF), 90ns(5V), 120ns(3.3V), 150ns(2.7V) 12:120ns(5V), 150ns(3.3V) 170ns(2.7V)
~ ul
Operating Temperature `Blank = 0C - +7O"C H = -40C - +85"C _
Pat kage T = 40-Lead TSOP R = 40-Lead TSOP(Reverse N = 44-Lead PSOP B = 42 or 48-Ball CSP
Bend)
)ption 1
Order Code LH28FOO8SCFbL85
V,,=2.7-3.6V 5OpF load, 1.35V I/O Levels LH28F008SC-L150
Valid Operational Combinations v,,=3.3*0.3v vc+.o*o.5v 1OOpF load, 5OpF load, TTL l/O Levels 1.5V I/O Levels LH28F008SC-L120 LH28F008SC-L90
Vcc=5.0~0.25V 3OpF load, 1.5V I/O Levels LH28F008SC-L85
Rev. 1.0
SHARP
8 Package and packing
-
LHF08CH2 specification 1
1
1. Package Outline Specification Refer to drawing No.AA 2. Markings 2 - 1. Marking contents ( 1) Product name : ( 2 ) Company name : (3) Date code (Example) Y Y WW
1 1 12
LH28F008SCR-L85 SHARP xxx Indicates the product was manufactured
(Lower (4) The marking of "JAPAN" indicates the country 2 - 2. Marking layout Refer drawing No.AAl 112 (This layout does not define the dimensions of marking 3.
two digits
of the year.)
of origin.
character
and mark ing position.)
Pack ing Specification (Dry packing for surface mount packages) Dry packing is used for the purpose of maintaining IC quality after mounting packages on the PCB (Printed Circuit Board), When the epoxy resin which is used for plastic packages is stored at high humidity, it may absorb 0.15% or more of its weight in moisture. If the surface mount type package for a relatively large chip absorbs a large amount of moisture between the epoxy resin and insert material (e.g. chip,lead frame) this moisture may suddenly vaporize into steam when the entire package is heated during the soldering process (e.g. VPS). This causes expansion and results in separation between the resin and insert material, and sometimes cracking of the package. This dry packing is designed to prevent the above problem from occurring in surface mount packages. - 1. Packing Materials Material Name Material Specificaiton Purpose Conductive plastic (50devices/tray) Fixing of device Tray _____________.__________________________--~-----~~---~~~----~------~-~----~~-----~~~~-~-----~~~~---~~~~--..----~.----~------.---------------------_____ _ __ Upper cover tray Conductive plast ic (ltray/case) Fixing of device ________________________________________---------.---------------------------------------------------___--____-____-_________________________---_ ___ _._. __ Laminated aluminum bag Aluminum polyethylene (lbag/case) Drying of device ________________________________________-------------------------------------------------------------------------------------------------------------------. Desiccant Silica gel Drying of device __._____________________________________---.---------. ._______________________________________~~~~~~~~~.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ P P band Polypropylene (3pcs/case) Fixing of tray ________________________________________~~-~~~~---~~~---~~~~~~~~~~~~~~~~~~~~~~~~.~~~~~~~.~~~~~~~~.~~~~~.~~~~~~~~~~~~~~~~~~~~ Inner case Card board (500devices/case) Packaging of device ________________________________________~~.--~~..--~~~--~~~~~---~~~~.--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.~~~~~-~~~~~~-~~~~~ Label Paper Indicates part number,quantit] and date of manufacture ,____________.______~~~~~..~~~~..~~~~~~.~~~~~~~~~~.~.~~~~~~.~~~~~~.~~~~~~~.~~~~~~~~~~.~.~~~~~~...~~~~...~~~~~.~.~~~~.~~~~~~.~~~~~~ Card board Outer case Cuter packing of tray (Devices shall be placed into a tray in the same direction.)
SHARP
3 - 2. Outline dimension Refer to attached of tray drawing
LHF08CH2
42
4. 4-l.
Storage
and Opening of Dry Packing the dry packing
Store under conditions shown below before opening ( 1) Temperature range : 5-40C (2) Humidity : 80% RH or less
4 - 2.
Notes on opening the dry packing (1) Before opening the dry packing, prepare a working table grounded against ESD and use a grounding strap. (2) The tray has been treated to be conductive or anti-stat i device is transferred to another tray, use a equivalent
which
is
c. If the tray.
4-3.
Storage after opening the dry packing Perform the following to prevent absorption of moisture after opening. (1) After opening the dry packing, store the ICs in an environment with a temperature of 5-25C and a relative humidity of 60% or less and mount ICs within 72 hours after opening dry packing. Baking (drying) before mounting ( 1) Baking is necessary (A) If the humidity indicator in the desiccant becomes pink (B) If the procedure in section 4-3 could not be performed ( 2) Recommended baking conditions If the above conditions (A) and (B) are applicable, bake it before mounting, The recommended conditions are 16-24 hours at 120C. Heat resistance tray is used for shipping tray. Mount Conditions Please perform the following quality.
4 -4.
5.
Surface
conditions
when mounting
ICs not to deteriorate
IC
5-l .Soldering conditions(Tbe following conditions are valid only for one time soldering.) Temperature and Duration Measurement Point Mounting Method Reflow soldering Peak temperature of 230C or less, IC package (air) duration of less than 15 seconds. surface 200C or over,duration of less than 40 seconds. Temperature increase rate of l--4'Vsecond _______.__________._____________________-------------------.-------------------------------------------------------. ___________________._____________ Manual soldering 260C or less, duration of less IC outer lead (soldering iron) than 10 seconds. surface
5 - 2.
for removal of residua 1 flux Cond itions Ultrasonic washing power : 25 Watts/liter (1) Washing time : Total 1 minute (2) Solvent temperature : 15-40C (3)
or less maximum
SHARP
LHF08CH2
LH28F008SCR- 5 L8
JAPAN YYWW xx
X
0 . h) ul It \r.
20. 0+-o. 3 18. 4&O. 2 t-
ASE PLANE
SEE DETAIL
A
DETAIL A
;I% j
4ME $SOP40-P-lOZO(R
!J-FttJz
[ TIN-LEAC Ikii*
`1S~f~9);~b-'iM~~,t18~~ll~\bq)lff3.
do not include burr
LEAD FINISH j PLATING #{Z j MAWING NO. i AA1112 UNIT ! mm
NOTE Plastic body dimensions of resin.
SHARP
LHF08CH2
44
mq
qAME\TSOP40-1020TCM-RH DRAWING NO. j CV644 qqiL UNIT j 1 mm
tlw
NOTE
SHARF,
LHF708CH2
Flash Noises generated Such noises, commands, To protect operating appropriate: 1) Protecting When a lock bit using this section(locked By controlling For further data feature, section) false in specific the flash block bit block block space is protected section). against overwriting. into the lock bit By can memory setting. can be locked/unlocked block bit 4.9 and 4.10) through and control the software. ing of RP#, refer can be divided program memory LHFXXCXX family having a level Data Protection the limit specified in the spec ificat may be interpreted on may be
45
exceeding operating
under specific causing with undesired
conditions
on some systems. as false systems designs, as
when induced onto WEStsignal the data stored the flash in the flash memory should
or power supply, memory against
memory updating. unwanted overwriting, write protect have the following
is set,
the corresponding
and data section(unlocked blocks
The master
be used to prevent
RI%, desired information
on setting/resetting (See chapter
to the specification. 2) Data protection When the level flashmemory write protected. voltage,
through
Vpp voltage), write operation on the intheblocksarecompletely (See chapter 6.2.3. )
of Vpp is lower than VPPLK (lockout is disabled.
All blocks are lockedandthedata refer RP# to the specification.
For the lockout 3) Data protect transition, blocks.
ion through operation
When the RP$ is kept write
low during
power up and power down sequence memory is disabled, write
such as vo 1 tage protecting 5.6 and6.2.7.) all
on the flash refer
For the detai 1s of RPB control,
to the specification.
(See chapter
Rev 1.3

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